[Problem] Taktprobleme bei 3 S2M an einer Patton 4960

s-art · 25 Jul 2012

Hallo zusammen,

in letzter Zeit häufen sich Probleme an dem Patton 4960.
Vor der Umstellung hatte ich bis zu 3 S2M von Vodafone an dem Gerät.
Zumindest gab es zu der Zeit keine "Totalaussetzer" - sprich ein S2M fällt total aus
und nur Netzstecker ziehen hilft.

Vor einige Zeit ist eine der Vodafone-Leitungen einer Telekom-S2M gewichen.
Mit dem Ergebnis, dass sich genau diese Leitung der DTAG (gefühlt) alle 2-3 Monate ins Nirvana verabschiedet.
Die anderen Leitungen sind einwandfrei im Betrieb.

Zur Info hier der entsprechende Teil der config:

Die Ports sind derzeit so konfiguriert.

Code:

port e1t1 0 0
  port-type e1
  clock auto
  framing crc4
  encapsulation q921

  q921
    uni-side auto
    encapsulation q931

    q931
      protocol dss1
      uni-side user
      bchan-number-order ascending
      encapsulation cc-isdn
      bind interface IF_E1_00 switch

port e1t1 0 0
  no shutdown

port e1t1 0 1
  port-type e1
  clock auto
  framing crc4
  encapsulation q921

  q921
    uni-side auto
    encapsulation q931

    q931
      protocol dss1
      uni-side user
      bchan-number-order ascending
      encapsulation cc-isdn
      bind interface IF_E1_01 switch

port e1t1 0 1
  no shutdown

port e1t1 0 2
  port-type e1
  clock auto
  framing crc4
  encapsulation q921

  q921
    uni-side auto
    encapsulation q931

    q931
      protocol dss1
      uni-side user
      bchan-number-order ascending
      encapsulation cc-isdn
      bind interface IF_E1_02 switch

port e1t1 0 2
  no shutdown

port e1t1 0 3
  port-type e1
  clock auto
  framing crc4
  shutdown

Die Fehler im debug sind (debug e1t1 error):

Code:

15:33:08  E1T1EV> [e1t1 0 0 2] HDLC TX FIFO empty
15:33:08  E1T1EV> [e1t1 0 0 2] HDLC TX sending 4 bytes (complete)
15:33:08  E1T1EV> [e1t1 0 0 2] Int 0x00 0x08 0x00
15:33:08  E1T1EV> [e1t1 0 0 2] HDLC RX ready: 4 bytes (complete)
15:33:08  E1T1EV> [e1t1 0 0 2] HDLC TX FIFO empty
15:33:08  E1T1EV> [e1t1 0 0 2] HDLC TX sending 4 bytes (complete)
15:33:08  E1T1EV> [e1t1 0 0 2] Int 0x00 0x08 0x00
15:33:08  E1T1EV> [e1t1 0 0 2] HDLC RX ready: 4 bytes (complete)
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC TX sending 13 bytes (complete)
15:33:09  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC TX sending 20 bytes (complete)
15:33:09  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:09  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 9 bytes (complete)
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:09  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:13  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:13  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 32 bytes (incomplete)
15:33:13  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:13  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:13  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:13  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:15  E1T1ER> [e1t1 0 0 0] BIT SLIP DETECTED. LOCAL CLOCK TOO SLOW

15:33:17  E1T1EV> [e1t1 0 0 1] Int 0x00 0x08 0x00
15:33:17  E1T1EV> [e1t1 0 0 1] HDLC RX ready: 4 bytes (complete)
15:33:17  E1T1EV> [e1t1 0 0 1] HDLC TX FIFO empty
15:33:17  E1T1EV> [e1t1 0 0 1] HDLC TX sending 4 bytes (complete)
15:33:17  E1T1EV> [e1t1 0 0 1] HDLC TX FIFO empty
15:33:17  E1T1EV> [e1t1 0 0 1] HDLC TX sending 4 bytes (complete)
15:33:17  E1T1EV> [e1t1 0 0 1] Int 0x00 0x08 0x00
15:33:17  E1T1EV> [e1t1 0 0 1] HDLC RX ready: 4 bytes (complete)
15:33:18  E1T1EV> [e1t1 0 0 2] HDLC TX FIFO empty
15:33:18  E1T1EV> [e1t1 0 0 2] HDLC TX sending 4 bytes (complete)
15:33:18  E1T1EV> [e1t1 0 0 2] Int 0x00 0x08 0x00
15:33:18  E1T1EV> [e1t1 0 0 2] HDLC RX ready: 4 bytes (complete)
15:33:23  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:23  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:23  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:23  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:23  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:23  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 32 bytes (incomplete)
15:33:23  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:23  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:23  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:23  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:27  E1T1EV> [e1t1 0 0 1] Int 0x00 0x08 0x00
15:33:27  E1T1EV> [e1t1 0 0 1] HDLC RX ready: 4 bytes (complete)
15:33:27  E1T1EV> [e1t1 0 0 1] HDLC TX FIFO empty
15:33:27  E1T1EV> [e1t1 0 0 1] HDLC TX sending 4 bytes (complete)
15:33:27  E1T1EV> [e1t1 0 0 1] HDLC TX FIFO empty
15:33:27  E1T1EV> [e1t1 0 0 1] HDLC TX sending 4 bytes (complete)
15:33:27  E1T1EV> [e1t1 0 0 1] Int 0x00 0x08 0x00
15:33:27  E1T1EV> [e1t1 0 0 1] HDLC RX ready: 4 bytes (complete)
15:33:28  E1T1EV> [e1t1 0 0 2] HDLC TX FIFO empty
15:33:28  E1T1EV> [e1t1 0 0 2] HDLC TX sending 4 bytes (complete)
15:33:28  E1T1EV> [e1t1 0 0 2] Int 0x00 0x08 0x00
15:33:28  E1T1EV> [e1t1 0 0 2] HDLC RX ready: 4 bytes (complete)
15:33:28  E1T1EV> [e1t1 0 0 2] HDLC TX FIFO empty
15:33:28  E1T1EV> [e1t1 0 0 2] HDLC TX sending 4 bytes (complete)
15:33:28  E1T1EV> [e1t1 0 0 2] Int 0x00 0x08 0x00
15:33:28  E1T1EV> [e1t1 0 0 2] HDLC RX ready: 4 bytes (complete)
15:33:29  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 17 bytes (complete)
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC TX sending 13 bytes (complete)
15:33:29  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:29  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 9 bytes (complete)
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:29  E1T1EV> [e1t1 0 0 0] HDLC TX sending 13 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)

15:33:30  E1T1ER> [e1t1 0 0 2] BIT SLIP DETECTED. LOCAL CLOCK TOO SLOW

15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 32 bytes (incomplete)
15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 12 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX sending 13 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 9 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX sending 13 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 32 bytes (incomplete)
15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC TX sending 13 bytes (complete)
15:33:30  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:30  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)


15:33:32  E1T1ER> [e1t1 0 0 1] BIT SLIP DETECTED. LOCAL CLOCK TOO SLOW

15:33:37  E1T1EV> [e1t1 0 0 1] Int 0x00 0x08 0x00
15:33:37  E1T1EV> [e1t1 0 0 1] HDLC RX ready: 4 bytes (complete)
15:33:37  E1T1EV> [e1t1 0 0 1] HDLC TX FIFO empty
15:33:37  E1T1EV> [e1t1 0 0 1] HDLC TX sending 4 bytes (complete)
15:33:38  E1T1EV> [e1t1 0 0 2] Int 0x00 0x08 0x00
15:33:38  E1T1EV> [e1t1 0 0 2] HDLC RX ready: 4 bytes (complete)
15:33:38  E1T1EV> [e1t1 0 0 2] HDLC TX FIFO empty
15:33:38  E1T1EV> [e1t1 0 0 2] HDLC TX sending 4 bytes (complete)
15:33:40  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:40  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)
15:33:40  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:40  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)


15:33:41  E1T1ER> [e1t1 0 0 0] BIT SLIP DETECTED. LOCAL CLOCK TOO SLOW


15:33:42  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:42  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 32 bytes (incomplete)
15:33:42  E1T1EV> [e1t1 0 0 0] Int 0x00 0x08 0x00
15:33:42  E1T1EV> [e1t1 0 0 0] HDLC RX ready: 4 bytes (complete)
15:33:42  E1T1EV> [e1t1 0 0 0] HDLC TX FIFO empty
15:33:42  E1T1EV> [e1t1 0 0 0] HDLC TX sending 4 bytes (complete)

Für mich sieht das nach einem Problem bei der Taktung aus, durch die Kombination von 2 Anbietern.
Sollte eigentlich der Wert clock auto (wie im Handbuch beschrieben) umgestellt werden auf slave?
Änderungen kann ich leider nur Nachts durchführen, das Testen kann also immer mal etwas dauern.

Als weitere Info (show port e1t1 detail 5):

Code:

Port: e1t1 0 0 0
================

  Clock:                                Auto
  Higher layer clock preference:        Slave
  Line Code:                            HDB3
  Framing:                              Multiframe with CRC4

IDT 82P228x
===========

  Type:                                 E1
  Port State:                           Enabled
  Link State:                           Active
  Clock:                                Slave
  Line Code:                            HDB3
  Framing:                              CRC4
  Loopback:                             Disabled
  Application:                          Short-Haul
  CAS channels:                         0
  Red alarm:                            Off
  AIS alarm:                            Off
  Basic Framing:                        yes
  Multi Framing:                        yes
  Crc4 to Non-Crc4 Interworking:        no
  Bit Slips (local clock too fast):     0
  Bit Slips (local clock too slow):     929
  Interrupt Counter:                    6851
  Timer interrupts:                     24090
  AIS interrupts:                       0
  Link Up events:                       1
  Link Down events:                     0
  HDLC RX calls:                        13709
  HDLC TX calls:                        5774
  Rx Frames:                            5774
  Rx Bytes:                             73738
  Tx Frames:                            5774
  Tx Bytes:                             46774
  Rx FIFO Errors 1:                     0
  Rx FIFO Errors 2:                     0
  Rx FIFO Errors 3:                     0
  Rx FIFO Empty (First):                1
  Rx FIFO Empty (Consecutive):          6850
  Rx FIFO Invalid Short Frames:         0
  Rx FIFO Invalid Long Frames:          0
  Rx Read Loop Errors:                  0

  HDLC Channel: 1
  ---------------

    TX packets:                         5774
    TX bytes:                           46774
    TX underruns:                       0
    TX curr. queued packets:            0
    TX max queued packets:              1
    RX packets:                         5774
    RX bytes:                           73738
    RX frame too big:                   0
    RX frame invalid:                   0
    RX checksum errors:                 0
    RX overflows:                       0
    RX no buffer available:             0
    RX ready queue overflows:           0
    RX curr. queued packets:            0
    RX max queued packets:              1

  Impedance:                            120 Ohm

Port: e1t1 0 0 1
================

  Clock:                                Auto
  Higher layer clock preference:        Slave
  Line Code:                            HDB3
  Framing:                              Multiframe with CRC4

IDT 82P228x
===========

  Type:                                 E1
  Port State:                           Enabled
  Link State:                           Active
  Clock:                                Slave
  Line Code:                            HDB3
  Framing:                              CRC4
  Loopback:                             Disabled
  Application:                          Short-Haul
  CAS channels:                         0
  Red alarm:                            Off
  AIS alarm:                            Off
  Basic Framing:                        yes
  Multi Framing:                        yes
  Crc4 to Non-Crc4 Interworking:        no
  Bit Slips (local clock too fast):     0
  Bit Slips (local clock too slow):     929
  Interrupt Counter:                    3887
  Timer interrupts:                     24089
  AIS interrupts:                       0
  Link Up events:                       1
  Link Down events:                     0
  HDLC RX calls:                        7774
  HDLC TX calls:                        3857
  Rx Frames:                            3857
  Rx Bytes:                             17473
  Tx Frames:                            3857
  Tx Bytes:                             16880
  Rx FIFO Errors 1:                     0
  Rx FIFO Errors 2:                     0
  Rx FIFO Errors 3:                     0
  Rx FIFO Empty (First):                0
  Rx FIFO Empty (Consecutive):          3887
  Rx FIFO Invalid Short Frames:         0
  Rx FIFO Invalid Long Frames:          0
  Rx Read Loop Errors:                  0

  HDLC Channel: 1
  ---------------

    TX packets:                         3857
    TX bytes:                           16880
    TX underruns:                       0
    TX curr. queued packets:            0
    TX max queued packets:              1
    RX packets:                         3857
    RX bytes:                           17473
    RX frame too big:                   0
    RX frame invalid:                   0
    RX checksum errors:                 0
    RX overflows:                       0
    RX no buffer available:             0
    RX ready queue overflows:           0
    RX curr. queued packets:            0
    RX max queued packets:              2

  Impedance:                            120 Ohm

Port: e1t1 0 0 2
================

  Clock:                                Auto
  Higher layer clock preference:        Slave
  Line Code:                            HDB3
  Framing:                              Multiframe with CRC4

IDT 82P228x
===========

  Type:                                 E1
  Port State:                           Enabled
  Link State:                           Active
  Clock:                                Slave
  Line Code:                            HDB3
  Framing:                              CRC4
  Loopback:                             Disabled
  Application:                          Short-Haul
  CAS channels:                         0
  Red alarm:                            Off
  AIS alarm:                            Off
  Basic Framing:                        yes
  Multi Framing:                        yes
  Crc4 to Non-Crc4 Interworking:        no
  Bit Slips (local clock too fast):     1
  Bit Slips (local clock too slow):     928
  Interrupt Counter:                    4005
  Timer interrupts:                     24089
  AIS interrupts:                       0
  Link Up events:                       1
  Link Down events:                     0
  HDLC RX calls:                        8010
  HDLC TX calls:                        3901
  Rx Frames:                            3901
  Rx Bytes:                             21759
  Tx Frames:                            3901
  Tx Bytes:                             19257
  Rx FIFO Errors 1:                     0
  Rx FIFO Errors 2:                     0
  Rx FIFO Errors 3:                     0
  Rx FIFO Empty (First):                0
  Rx FIFO Empty (Consecutive):          4005
  Rx FIFO Invalid Short Frames:         0
  Rx FIFO Invalid Long Frames:          0
  Rx Read Loop Errors:                  0

  HDLC Channel: 1
  ---------------

    TX packets:                         3901
    TX bytes:                           19257
    TX underruns:                       0
    TX curr. queued packets:            0
    TX max queued packets:              1
    RX packets:                         3901
    RX bytes:                           21759
    RX frame too big:                   0
    RX frame invalid:                   0
    RX checksum errors:                 0
    RX overflows:                       0
    RX no buffer available:             0
    RX ready queue overflows:           0
    RX curr. queued packets:            0
    RX max queued packets:              2

  Impedance:                            120 Ohm

Port: e1t1 0 0 3
================

  Clock:                                Auto
  Higher layer clock preference:        Master
  Line Code:                            HDB3
  Framing:                              Multiframe with CRC4

IDT 82P228x
===========

  Type:                                 E1
  Port State:                           Disabled
  Link State:                           Inactive
  Clock:                                Slave
  Line Code:                            HDB3
  Framing:                              CRC4
  Loopback:                             Disabled
  Application:                          Short-Haul
  CAS channels:                         0
  Red alarm:                            Off
  AIS alarm:                            Off
  Basic Framing:                        no
  Multi Framing:                        no
  Crc4 to Non-Crc4 Interworking:        no
  Bit Slips (local clock too fast):     0
  Bit Slips (local clock too slow):     0
  Interrupt Counter:                    0
  Timer interrupts:                     0
  AIS interrupts:                       0
  Link Up events:                       0
  Link Down events:                     0
  HDLC RX calls:                        0
  HDLC TX calls:                        0
  Rx Frames:                            0
  Rx Bytes:                             0
  Tx Frames:                            0
  Tx Bytes:                             0
  Rx FIFO Errors 1:                     0
  Rx FIFO Errors 2:                     0
  Rx FIFO Errors 3:                     0
  Rx FIFO Empty (First):                0
  Rx FIFO Empty (Consecutive):          0
  Rx FIFO Invalid Short Frames:         0
  Rx FIFO Invalid Long Frames:          0
  Rx Read Loop Errors:                  0
  Impedance:                            120 Ohm

Sollten noch Fragen dazu sein oder andere Infos nötig - her damit.
Danke.

Gruß
Jörg

al3x · 13 Aug 2012

Hi Jörg,

wie sieht deine komplette running.cfg aus? Wir haben drei vollwertige S2M an einer Smartnode 4960 angeschlossen und keine Probleme mit dem Clock.
Stimmt bei dir die "clock source"?
Am port e1t1 0 0 ist der clock auf "slave" eingestellt und dazu die system clock-source 1 e1t1 0 0 .
An den ports e1t1 0 1 und e1t1 0 2 ist der clock auf "auto" .

Gruß
Alex

s-art · 6 Sep 2012

Hallo Alex,

danke für deine Info. Besten Dank dafür!
Eine kleine Verbesserung gab es schon nach der Abschaltung der 3. nicht mehr benötigen Leitung.
Ich habe deine config angepasst. Die Einstellung am port e1t1 clock von auto auf slave hat geholfen.
Jetzt arbeiten DTAG und Vodafone wieder brav zusammen.

Gruß
Jörg

[Problem] Taktprobleme bei 3 S2M an einer Patton 4960

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